The invention relates to a current memory cell comprising a fine MOS memory transistor and a coarse MOS memory transistor connected in series between two power supply rails, an input coupled to the junction of the drain electrodes of the fine and coarse memory transistors via a switch which is closed during a first portion of a clock period, a second switch connected between the gate and drain electrodes of the coarse memory transistor which is closed during a first part of the first portion, a third switch connected between the gate and drain electrodes of the fine memory transistor which is closed during a second part of the first portion and an output coupled to the junction of the drain electrodes of the coarse and fine memory transistors via a fourth switch which is closed during a second portion of the clock period.
The invention further relates to a circuit arrangement comprising a plurality of current memory cells.
Such a current memory cell is disclosed in EP-A-608936. These current memory cells are normally designed such that under quiescent conditions the sum of the voltage drops across the diode connected coarse and fine transistors matches the supply voltage. That is, V.sub.gsn +V.sub.gsp =V.sub.dd. This condition is ensured by the choice of transistor saturation voltages which together with the memory capacitance determines the memory cell's signal to noise ratio. However, the layout parasitic capacitance sometimes gives larger total memory capacitance than is needed to meet the signal to noise ratio specification and adherence to the above condition results in an over design of signal to noise ratio and an undesirably high power consumption.
If the alternative strategy of reducing V.sub.gsn and V.sub.gsp to achieve the desired signal to noise ratio while obtaining a lower power consumption is chosen, this results in the sum of V.sub.gsn and V.sub.gsp being less than V.sub.dd. Under these circumstances, during operation of the memory cell, there is a voltage jump at the summing node from the coarse input phase to the fine input phase and again from the fine input phase to the output phase. This produces undesirable behaviour including increased power consumption and harmonic distortion.